This site will be the beginning of your journey through 238s lab, Xilinx, and VHDL. Here is where we will take the novice who can turn on the computer and find the mouse (nine out of ten times) through a simple VHDL Xilinx project. Below is the schematic needed to be implemented. By this time, the purpose of all of the parts and their functions should be familiar.

VHDL has three styles of implementing designs -- data flow, structural or behavioral. Any decent VHDL book can give an in-depth study of the differences between these styles. One such VHDL book written specifically for the Xilinx software is "Introductory VHDL" by Sudhakar Yalamanchili (ISBN 0-13-080982-9). Behavioral was choosen for this particular lab. There are also some really good free tutorials available through the links page on this web site. Below is the code for this project. Certain attributes such as in, out, and the signals (A, B, C, Y) should be easily associated with the picture above.

There are actually two sections of code for this lab. The first is the behavioral description of what the project is to do. Download the code here (read it and analize it!!). The second set of code is the test bench. As its name implies, it is used to test the project. It is used to specify how your inputs are supposed to behave and then you observe your outputs. Here is the test bench code.

On the computer, start the Xilinx Project Navigator. Click on Start, go to Programs, Xilinx ISE 5 and click on Project Navigator or double click on the icon on the desktop. Choose File, New Project. This will bring up a screen like the one below. Choose a directory for your file and name it. Use the same settings as in the picture. Why these settings have been chosen will be explained in more detail as the labs progress. This is just a a quick overview. Once the correct options have been chosen, click OK.

Project Navigator should now be showing a newly created project. Now's the time to add the VHDL code files. This lab has all the code included. Very soon the code writing will become the responsibilty of the student, so spend some time anaylizing the code. Determine what it is actually doing. Once again, many examples and tutorials on VHDL can be found through most any Internet search engine or on the links section of this website. It is the mainstay of computer engineers' world.

Click on Project, New Source. A screen like the one below should appear. Fill it in accordingly.

When next is clicked, a screen that says Define VHDL Source comes up. This assistant will not be utilized so click Next and Finish. The screen on the computer should now have the completed shell of the vhdl within the upper right hand window of the screen.

Since the VHDL has been supplied, this shell will not be needed. Highlight all the VHDL code and delete it. Go back to the top of this page and copy all the red code under the Few Gates Code and paste it into the project. Note the way the software color codes the code (green for comments, blue for keyword/reserved words, etc.). This feature can be used as an error detection technique. It can sometimes help find code problems. Now we need to add the testbench code. Once again go to Project, New source. This time choose VHDL testbench as shown below. Notice the naming technique used on the testbench file ("_tb.vhd").

Once again, click Next and Finish. Delete the existing code and paste in the red code above listed as Few Gates Test Bench Code. Click the Save All icon in the upper portion of the screen.

When looking into the left hand portion of the screen, notice how the testbench code falls below the main program in a hierarchical level. This is based on the concept that the testbench would serve no purpose without the main code. The testbench serves only to test the main code. Of course, at this time, the code is assumed to be syntactically correct because it was a given. However, it is good practice to always do a syntax check. A correct syntax check will not guarantee that the program will perform as expected, but it will ensure that there are no missing semi-colons, etc. Unfortunately, the code's logic could still contain errors that will keep the program from working correctly.

Highlight the fewgates code (in the Sources in Project box) and then expand the Synthesize section within the Process window and double click on Check Syntax. The syntax check should indicate no errors. To see how it looks with errors, change some letters in the fewgates code and do the process again. A green check mark is conformation that the syntax check was successful.

The next step is to simulate this design. Simulation gives the ability to ensure a project does what is expected. This particular testbench is designed to run three different clock processes. This allows for all possible inputs on the A, B, and C input pins. The A clock runs at a certain rate. The B clock runs at twice that rate and the C clock runs at twice the rate of the B clock. To get to the simulation, the ModelSim simulator needs to be evoked. Click once on the testbench file to highlight it. Within the process window you will now notice a different set of processes available. Double click on Simulate VHDL Behavioral Model. This tells the Xilinx software to launch Modelsim and use the test bench file to test the main code.

Three new ModelSim windows will appear. For this lab, only the one titled Wave (a black screen with green lines) will be utilized. Expand it by clicking on the magnifying glass that says Zoom Full.

Now it can be seen that anytime A and B are low or C is high, Y will be high. This could be thought of in terms of voltages with the lower line being 0 volts and the elevated line being 5 volts. This will not always be the case as far as voltage levels is concerned (many devices are now running at much less than 5 volts) but it is good at this point to make it easier to understand. Click into the waveform to see a blue wave form that can be dragged across the time frames. This will show the input and output status at various times.

For many, this might have been their first exposure to a set of tools like these. Basically, all the process has done is decribe the behavior of a the above circuit using VHDL. The circuit could just as easily have been a traffic light or a remote control. The simulation tool was then implemented to verify that the code worked as expected.