Lab 6 Tutorial - Introduction to Accumulators, Floorplanner and Spartan XL FPGAs

This project will show you how to create a four bit accumulator. Here is a picture of how the tutorial project will work and how your assignment will fit into the picture.

Create a new project with the following properties. Your project name can be whatever you desire.

Here is a good trick that will save you a lot of grief later. You have just created a folder where your project will be stored. You can see that entire path by looking at the top of the project navigator window. As your projects continue to grow and contain more and more files, it is a good idea to keep all of your "source" files in a directory by themselves. This makes it easier to quickly isolate them from the multitude of files that are routinely created as part of the project. Go to Explorer and make a new directory within your project directory and put the following files into that directory.

top.vhd
accumvhd.vhd
accumvhd_tb.vhd
7_segment_controller.vhd

Go to Project, Add Source, and add all four files. Go slow and make sure you identify the files as VHDL modules or VHDL testbenches correctly. Three of them are VHDL modules and one of them (*_tb.vhd) is a VHDL Testbench. After this is complete the file hierarchy should look like this:

Now would be a good time for you to print out the VHDL files and read them for a while. A large portion of this project is understanding what the code is doing. Do not go any further until you are very clear on how the code works. As you can see from the picture above, the software is smart enough to recognize the structure of the project. It realizes that the testbench is not for the entire project but only for the accumulator portion of the project. This was done so that you could understand what the accumulator is doing. It is beyond the scope of this course to have you simulate the rest of the code. To demonstrate how an accumulator works, select accumvhd_tb.vhd and double click Simulate Behavioral VHDL Model.

As you can see from the simulation, when RST_H goes low and you get a rising edge on USER_SET, the accumulator (q) begins to add. RST_H means reset asserted high. Asserted high means the signal expects a high to do what it is intended to do. In this case, if RST_H is high, the project is forever in a reset state. Since the input (d) is "1", the accumulator continues to increase by one each time it sees a rising edge of USER_SET. When you are comfortable with the functioning of the accumulator go ahead and close the Modelsim software.

We now need to assign the pins. Go to Project, New Source. Choose Implementation Constraints File. Name the file top.ucf and click Next. In Associate with Source choose top and click Next and Finish. In Processes for Current Source expand User Constraints. Double click Edit Constraints (Text).

Paste in the following code:

#
NET"RST_H"LOC = P84;
NET"USER_SET" LOC = P15;
NET "DATA<0>" LOC = P57;
NET "DATA<1>" LOC = P59;
NET "DATA<2>" LOC = P62;
NET "DATA<3>" LOC = P65;
#NET "DATA<4>" LOC = P67;
#NET "DATA<5>" LOC = P75;
#NET "DATA<6>" LOC = P78;
#NET "DATA<7>" LOC = P80;
NET "SBASE_OUT_H<0>" LOC = P100;
NET "SBASE_OUT_H<1>" LOC = P103;
NET "SBASE_OUT_H<2>" LOC = P94;
NET "SBASE_OUT_H<3>" LOC = P96;
NET "SSEG_OUT_H<6>" LOC = P58;
NET "SSEG_OUT_H<5>" LOC = P60;
NET "SSEG_OUT_H<4>" LOC = P63;
NET "SSEG_OUT_H<3>" LOC = P66;
NET "SSEG_OUT_H<2>" LOC = P74;
NET "SSEG_OUT_H<1>" LOC = P77;
NET"SSEG_OUT_H<0>" LOC = P79;
# #

Click save.

In .ucf files unlike traditional VHDL files comments are made with "# " instead of " --". Data 4-7 is commented out becuase they were not needed for this project. However, you will need them for the lab assignment. You can find the pin outs for this chip here. The pin outs for the various peripherals are found at www.digilentinc.com.

The general flow for the next couple of parts is very similar to the CPLD labs. We will synthesize and then implement. Here is a Xilinx slide to give a pictorial view of what we are doing.

If you look at the blocks on the left you can see where we have gone from HDL (hardware definition language) by using VHDL. We are now going to use XST for synthesis. As you can see from the picture, synthesis will take us from our HDL to a netlist. We will then implement which will convert our netlist into a bit file by means of the back end Xilinx place and route tools.

First, double click on the circular Synthesize icon (ensure you have top.vhd highlighted). It will begin to synthesize the entire project by combining all the files to form the single netlist. If you were not sure that the project was going to be clean up to this point, you would want to expand the synthesize area and double click one item at a time. I would advise doing this when you are debugging your portion of the project. You may receive some warnings about nets not being attached and the synthesis should complete with a yellow icon or a green check mark. Both are fine.

Now double click on the circular icon next to Implement Design. After a few minutes the software should succeed with placing and routing of your netlist into a .bit file, ready to transfer to the device. For many designs this is the long portion of the project. For large scale projects directed towards multimillion gate FPGAs, it could take hours or days to do the place and route. For VirtexE2000 (2 million gate devices) it is recommended that you have 2G of RAM in your computer to handle the processing. It is very computer demanding.

Before we proceed to the final step of programming the device, you should ensure that the switch box on top of the computer is set to FPGA and that the power strip is turned on. This is also where zip disks are essential. Your project is now over three Meg in size.

Right click on Generate Programming File and click Properties. Select the Readback Options tab.

Click the check box to the right of Create ReadBack Data Files. Then click the check box to the right of Create Mask File. Click Ok.

Double Click Generate Programming File. Expand Generate Programming File and double click Configure Device (iMPACT).

An Operation Mode Selection dialog box will come up. Choose Configure Devices and click Next. Then a Configure Devices dialog box will pop up. Choose Boundary-Scan Mode and click Next. Then a Boundary-Scan Mode Selection dialog box will come up. Choose Automatically connect to cable and identify Boundary-Scan chain and click Finish. Click Ok.

Browse to top.bit and click Open.

You might get a warning. Just click Ok. Now right click on the chip and click Program. Accept all of the defaults in the Program Options dialog and click Ok .

When you see that programming has succeeded, you can begin testing the accumulator.

Remember that if you push the switches to the right, they are high, and if you push them to the left, they are low. Push SW2 to the right and push SW1, 3, and 4 to the left. This means 2.

You can set the switches so that you can add any number between 0 and 15 to the accumulator.

Toggle USER_SET (BTN1). Note: There are two BTN1s, so be careful. Look at the illustration below.

You should see 02 on the display. As you continue to push USER_SET, it should continue to increment/accumulate until it gets to FF in hex at which point it will start over again. Unfortunately, even though these buttons are supposed to be debounced, I have found that some of the boards in the lab have buttons that are a little dirty. What you may find is that when you push the button once, it may register more than one push. This is not overly critical at this point. It is much more important that you see the flow of the project.

Push RST_H (the other BTN1, see below).

This will cause the accumulator to reset.

Now that you see how this portion of the finished project works, you should begin to understand your portion of the project. I used SW1-4, and two of the digits. You use SW5-8 and the other two digits. The two accumulators will be completely separate except for the USER_SET and RST_H buttons and the sharing of the seven-segment display. If you add 3 to my accumulator, it should have no impact on yours and vice versa. One more quick side journey before you receive your final assignment. I want to show you how the software configured the device. Close iMPACT (no need to save anything).

Expand Implement Design, Place & Route. Double click View/Edit Placed Design (Floorplanner).

This is a graphical representation of how the project was developed onto the chip. What you are looking at is an overhead view of the device. The outer ring is the input and output blocks (IOBs). Just as with CPLDs, this is how the device communicates with the outside world. All of the inner boxes are configurable logic blocks (CLBs). This is where all the data processing actually occurs.

Make sure that the Toggle Labels, Toggle Rubberbands and Toggle Resource Graphics buttons are selected (shown below).

Zoom in on the chip and click one of the CLBs.

You can see how this CLB is connected in your project. By double clicking, you can see how the whole project is interconnected.