Spartan-3E Starter Kit Board User Guide
How to install Xilinx's software
Lab 1 (09/01/08 - 09/06/08): Introduction to Discrete Digital Logic
Lab 2 (09/08/08 - 09/13/08): Part 1: Introduction to VHDL, ISE and ModelSim; Part 2: Basic VHDL language constructs. Concurrent signal assignment statements, components. READ RTL BOOK SECTION 2, UP TO SUBSECTION 2.2 (included), and SECTION 3, UP TO SUBSECTION 3.2.3 (included)
- Lab Manual Part 1/Tutorial
- Files for part 1: Source file , Testbench file and Ucf file
- Lab Manual Part 2/Tutorial
- Lecture notes - slides
- Additional slides about testbench
- Worksheet
Lab 3 (09/15/08 - 09/20/08): Introduction to VHDL II
Lab 4 (09/21/08 - 09/27/08): Sequential statements of VHDL. Process. Use of variables in sequential circuit description. Counters. READ RTL BOOK SUBSECTIONS 3.3 AND 3.5, SECTION 4 UP TO SUBSECTION 4.4 (included), SECTION 5 UP TO SUBSECTION 5.5 (included)
- Laboratory Manual/Tutorial
- Worksheet
- Lecture notes - slides
- Laboratory files: The source code is at the end of the Tutorial
Lab 5 (09/29/08 - 10/04/08): State machines
- Laboratory Manual/Tutorial
- Worksheet
- Lecture notes - slides
- Source files corresponding to the tutorial
Lab 5.5 (10/05/08 - 10/11/08)
Lab 6 (10/20/08 - 10/25/08): Finite/Algorithmic State Machines. Please read Sections 10.1 and 10.2
Lab 7 (11/02/08 - 11/08/08): More ASMs
Lab 8 (11/10/08 - 11/15/08): More ASMs - Repetitive-substraction division
Lab 9 (11/17/08 - 11/29/08): Two-function calculator
Final Project (Due 12/12/08 Before 5:00 PM): Attach the final project report to the notebook, which must include all the previous labs. Drop your notebook at room 217 (Hao He) or room 312 (Jorge)
