Spartan-3E Starter Kit Board User Guide
How to install Xilinx's software
Lab 1 (01/26/09 - 02/02/09): Introduction to Discrete Digital Logic
Lab 2 (02/02/09 - 02/09/09): Part 1: Introduction to VHDL, ISE and ModelSim; Part 2: Basic VHDL language constructs. Concurrent signal assignment statements, components. READ RTL BOOK SECTION 2, UP TO SUBSECTION 2.2 (included), and SECTION 3, UP TO SUBSECTION 3.2.3 (included). Be ready for a quiz at the beginning of lab hours.
- Lab Manual Part 1/Tutorial
- Files for part 1: Source file , Testbench file and Ucf file
- Lab Manual Part 2/Tutorial
- Lecture notes - slides
- Additional slides about testbench
- Worksheet
Lab 3 (02/16/09 - 02/23/09): Sequential statements of VHDL. Process. Use of variables in sequential circuit description. Counters. READ RTL BOOK SUBSECTIONS 3.3 AND 3.5, SECTION 4 UP TO SUBSECTION 4.4 (included), SECTION 5 UP TO SUBSECTION 5.5 (included)
- Laboratory Manual/Tutorial
- Worksheet
- Lecture notes - slides
- Laboratory files: The source code is at the end of the Tutorial
Lab 5 (03/02/09 - 03/09/09): State machines
- Laboratory Manual/Tutorial
- Worksheet
- Lecture notes - slides
- Source files corresponding to the tutorial
Lab 6 (03/23/09 - 03/30/09): Finite/Algorithmic State Machines. Please read Sections 10.1, 10.2, 10.5.1 and 10.5.2.
Lab 7 (03/30/09 - 04/06/09): More ASMs
Lab 8 (04/06/09 - 04/13/09): More ASMs - Repetitive-substraction division
Final Project (Due 05/08/09):
