Site last updated
9/12/03

                                      Implementing Flip-Flops

By this point you have completed five projects with Xilinx.   You should be starting to become familar with opening and working with projects.

Objectives:

1.  To familiarize yourself with the function of the D flip-flop and it's operation.

2.  To familiarize yourself with the function of the JK flip-flop and it's operation. 

3.  Implement  in Xilinx.  For Xilinx, you are going to simulate both of the above circuits.  We will provide you with large portions of the VHDL code.

4.  Create a T flip-flop using Xilinx and VHDL code.

1. D Flip-Flop.  A D flip-flop is a memory element that holds one bit of information.

Take a D flip-flop from your chip kit and verify its operation by comparing your outputs to the outputs that you predicted on your worksheet for a given set of inputs.  Have your hypothesis section of the worksheet filled out and verified by your TA prior to physically changing states on your chip. The truth table for the D flip-flop is given below.  Click here to obtain the complete data sheet.

2.  JK Flip-Flop.  Take a JK flip-flop from your chip kit and repeat the procedure.  Below is the truth table for the JK flip-flop. Which chart you use will depend on if you have a 7476 or a 74LS76 (low speed) but for our purposes, both charts will produce the same results.  Go here for the complete data sheet.

3.  Xilinx.  There are two parts. 

Part One.  Here is the code for the D flip-flop.  At the top of this section, some of the various aspects of the code has been explained.  You should complete this section on the D flip-flop and then return back here to complete the next section on the JK flip-flop.  The deliverables for the D flip flop are shown at the bottom of the code section. 

Part Two.  For the JK flip-flop, we will utilize your text book.  Do not do both flip-flops as one project.  This sometimes causes problems.  Make each one a separate project.  Problem 4-40 in your text calls for you to develop the code for a negative edged JK.  Even nicer for you is that this is a problem that has a solution at their web site.  The code they give you is for a negative edge-triggered JK.  Here is a picture of their code and their simulation.  Click here for a larger print version.

The problem is that your customer wants the following changes and it is your job as their engineer to update the design:

1.  Change your input names from CLK, J and K to CLK_H, J_H, and K_H (pronounced clock asserted high, J asserted high, and K asserted high).  This is a name style that lots of folks like since it tells them the logic level that is supposed to be there to provide a true case.

2.  Change from a negative edge trigger to a positive edge trigger.  Examine some of the Prentice Hall example code in your book and you should be able to see what you have to change.

3.  Use the exact same input waveforms to perform simulation on your new code.   This will be the major new learning portion of this lab.  In the past you have selected the "generic" clock inputs for your simulation (clicked on the little round buttons).  This time you are being asked to specify exactly when your inputs will change.  For this I will provide you a tutorial.  Once you have finished changes one and two above and have your code syntax checked and added to your project you should select the synthesis button.  Spartan XLs (the type we have at UNM) are some of the newest FPGAs in the world.  If we were to want to program our FPGAs, then we would choose them as our device option.  Go ahead and do so.  If you want to see more about the SpartanXL FPGA, go to the manufacturers web site or talk to Craig.

Select "Run".  The program will now go through the process of elaborating your design for it's final placement on a Spartan FPGA.  When this process is complete you should see a couple of blue warnings in the lower area and an "!" in the synthesis section.  Don't be overly concerned by this now.  It's cause will be understood when we do the FPGA lab.  Now you will need to go to the tutorial section to work through the simulation section and to get a list of your deliverables.

Click here to go to Lab 5 worksheet.

Click here to go to Lab 5 tutorial.

Click here to go to the D flip-flop assignment.