Site last updated
9/12/03

LAB 8 ASSIGNMENT

Objective: 

To understand the operation and control of an arithmetic logic unit (ALU) in terms of how its functions are selected, and how the inputs to and the outputs from an ALU are handled.

There are three parts associated with this lab.  Part one is an easy step-by-step tutorial explaining the procedure of how to take an archived project, download the files, and open it up through Xilinx's restore feature.  Once this project has been recreated, it can then be downloaded onto the FPGA board where the ALU's features can be tested and verified by you, the user.  This way, a better understanding of the ALU design can be obtained through hands-on experience.

The second section of this assignment involves copying some pre-designed VHDL code, creating a macro with this code, and inserting the macro into a schematic.  This new ALU design will then be downloaded onto the FPGA board, tested, and verified exactly like Part One.

The last part of this lab is the most time consuming, but the most challenging.  The code from Part Two will be studied, changed, and revised to meet specific ALU design requirements.  Again, as with the previous parts of this assignment, the project will be implemented and downloaded to the FPGA to test the different operations for correctness. 

PART 1

As with the previous tutorials, this one has easy to follow instructions that walk you through the restoring and downloading of this design.  The best advice is to try to get through Part 1 and Part 2 as quickly as possible since it is Part 3 that has the potential of taking up the most time.

After downloading the design, familiarize yourself with the design and operations of the ALU.  Operand inputs are generated from the first four slide switches, SW1 through SW4.  SW1 is the MSB and SW4 is the LSB.  When the switch is moved towards the edge of the board, it is considered a binary '1'.  After selecting a number with the first four switches, depress BTN1 (button #1) to load that number into register A.  The register will hold the number you input and act as a storage area.  Use these same switches to determine your next number and push BTN2.  This will then be loaded into register B.  Operands much be latched into the A and B registers before an operation can be performed.  Take notice that the seven-segment display shows the settings of the first four slide switches.  Once button #1 has been depressed, the first four LED's light up with the contents of register A.  The same thing happens when button #2 has been selected except this time it is LED5 through LED8 that are illuminated. 

When both registers have been loaded, the desired operation can then be selected by using SW5 through SW7 and then depressing BTN3 (keep this button depressed).  The results are displayed on the seven-segment display.  The results will be displayed only during the time that BTN3 is help down.  When you lift your finger off the button, there is no longer a LCD display   The following table depicts which number segment corresponds to which operation.

Now that the ALU results have been verified, try to do some basic questions:

What is Ch-6h?  (i.e.  what is C in hex minus 6 in hex?)

What is Eh and 3h?  (i.e.  what is bitwise E in hex ANDed with 3 in hex?)

Fill out questions 1) and 2) on the worksheet.

Part Two

This part is also explained in a step-by-step fashion in the tutorial.  Once the VHDL has been turned into a macro and downloaded onto the FPGA, verify that the behavior of the new design is the same as the table below:

Fill out questions 3) and 4) on the worksheet.

Part Three

Study the operation inputs from Part One.  Take notice that the first two operations are math operations, the next four operations are logical operations, and the last two operations are shift operations.  Now study the code given in Part Two and rewrite the VHDL so that the new operation inputs are:

Once your design has been implemented correctly, show your TA the working results and finish answering the questions on the worksheet.