Site last updated
9/12/03

Lab Three:  Multiplexers, Arithmetic, and IP Cores

Objectives:

By the time the student has completed this lab and it's associated tutorial, the student should be familiar with the following:

1)  Using multiplexers in circuit design.

2)  Using the Xilinx ISE software and ModelSim to create and verify the operation of a simple digital arithmetic design.

3)  Building on parts one and two to better understand one of the most fundamental blocks of a digital computer:  the full-adder.

4)  Designing complex circuits using limited resources.

5)  Using the Xilinx CORE Generator System to create designs in the Xilinx ISE design suite, and simulate them using ModelSim.

Part I:  Multiplexers

Here, you will be using multiplexers to implement a basic subtractor circuit.  The multiplexer you will be using is the 8-to-1 multiplexer.  You will need to decide how to best set up the control lines and inputs to derive the correct results.  It is suggested you use the following design process:
A)  Design the circuit on paper.
- Fill out the Karnaugh maps for subtractor.  Remember that it has three inputs:  X, Y, and B_IN, and the two outputs:  D, and B_out.  This means you will need two Karnaugh maps.

-  Design this circuit using the 8-to-1 multiplexers.  Look at your Karnaugh maps and decide how to best setup the control lines, and the eight input lines to generate the two correct outputs.

- Draw the logic diagram for the subtractor.  This will give you some idea of how much board space you will save when you implement the design using multiplexers, rather than basic logic gates.

B)  Implement your design on the prototyping boards in the laboratory.  Debug your design and then demonstrate it to your TA.

Part II:  Using Xilinx.

Here, you will take the circuit you designed in Part I, and implement it using the Xilinx ISE design suite.  Recall that we've shown you how to do this in the lab tutorial.  Multiplexers are represented in VHDL by case-statements.  In the 4-to-1 multiplexer example in the tutorial, that meant that we had a case statement with four possible valid results, looking like this:

   case XY_IN is
      when "00" => DIV_OUT <= BROW_IN;

Successfully completing the first half of the tutorial will be sufficient introduction in this case.  However, you will have the chance to develop your own VHDL and simulation testbench in the last part of the lab.

Part III:  Introduction to the Full-Adder, and Logic Design With Limited Resources.

Recall that in the lab lecture, we covered how to design an adder just using  multiplexers.  Recall how many components we saved implementing a subtractor using multiplexers in Part I of this lab.  However, for this part of the lab, we will require that you use either NAND gates, or Exclusive-OR gates to implement a full-adder.

In the digital design world, the engineer will not always be capable of obtaining the components he or she would like to use.  Customers may have a close relationship with a given semiconductor company, and thus, will require you to use that company's devices.  Or, a customer may want you to design a device to meet certain cost constraints,or environmental tolerances.  For this lab, you must develop and implement your full-adder utilizing only NAND gates, or Exclusive-OR gates.  Therefore, in this lab, paying close attention to your Karnaugh maps can offer handsome payoffs, in terms of the number of devices you end up using in your design.

Use the following design process to guide you in this part of the lab:

A)  Design the circuit on paper.
- Fill out the Karnaugh maps for the adder.  Remember that it must have three inputs:  A, B, and a Carry_in.  It will also have two outputs:  Sum, and Carry_Out.  Again, this means you will need two seperate Karnaugh maps, one for each output term.

-  Draw the resulting logic diagram.  Recall that each of those symbols would be 1/4 of a 7400 IC.  And with that in mind . . .

-  Map out how you plan to arrange the chips on the prototyping board.  Do this on a piece of paper.  When mapping the chips, try mapping along the following guidelines:.

- Logical organization.  That is, devices should not be scattered
randomly around the board.

- Wiring concerns.  The less your final design resembles a rat's nest,
the easier it will be to test and debug your circuit.

B)  Implement the circuit in lab.
-  Assemble the circuit on the prototyping boards in the laboratory.
-  Debug the resulting circuit, and verify it's function.
-  Demonstrate the successfully completed circuit to your TA.

Part IV:  Using The CORE Generator System.

For this part of the laboratory, you will be working exclusively in the ISE design suite.  Using the second part of the tutorial as your guide, create an ISE project and start the CORE Generator System.  You will need to set it up as shown below:

Create an 8-bit Registered Adder core for the Spartan. You will then need to write the VHDL top-level source file and the VHDL testbench to simulate it in ModelSim.

Before you write your testbench, read the datasheet to familiarize yourself with the input signals.

We will supply you with portions of the testbench.  However, you will be expected to write much of it on your own.

When writing your testbench, you should at least have the following:

-Add two small positive numbers together (say 00000110 and 00000001).
-Add a positive number (00000010) and a negative number (11111110).
-Add this number (011111111) and (00000001).  What happens?

Below is the basic framework of your testbench:

LIBRARY  IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

--Declaration of ModelSim libraries used
LIBRARY  UNISIM;
LIBRARY  XILINXCORELIB;

ENTITY testbench IS
END testbench;

ARCHITECTURE testbench_arch OF testbench IS
-- This is the one of the components we will be simulating.
-- You will supply the necessary component declaration here.

-- Here, we will be adding some signals.  Following the tutorial
-- Assign the ports from your component to the signals I furnish
-- below.

SIGNAL a_data_in : std_logic_VECTOR(7 downto 0);
SIGNAL b_data_in : std_logic_VECTOR(7 downto 0);
SIGNAL reset_in : std_logic;
SIGNAL clock_in : std_logic;
SIGNAL chip_enable : std_logic;
SIGNAL carry_in : std_logic;
SIGNAL sum_data_out : std_logic_VECTOR(8 downto 0);

-- Next, I will define a standard clock of 40 ns, or 25 MHz
-- (When you actually configure the FPGA and CPLD boards,
-- they have a minimum clock time of about this.)
--Defining the variable "CLK_PERIOD" to be
--equal to 20 nano seconds
constant CLK_PERIOD : time:= 40 ns;

BEGIN
-- Unit under test is the module complement.  Notice
-- that it is not case sensitive.  Here you will have the component
-- that you declared above.  Except in the port map, you will assign
-- the ports to the simulation signals I defined above.

-- Now I will define some of the basic processes.  I'm taking the easy ones.

master_clock : PROCESS
BEGIN
clock_in = '0';
wait for CLK_PERIOD / 2;
clock_in = '1';
wait for CLK_PERIOD / 2;
END PROCESS;

carry_in_forever : PROCESS
BEGIN
carry_in = '0';
wait for CLK_PERIOD;
carry_in = '0';
wait for CLK_PERIOD;
END PROCESS;

chip_enable_forever : PROCESS
BEGIN
chip_enable = '1';
wait for CLK_PERIOD;
chip_enable = '1';
wait for CLK_PERIOD;
END PROCESS;

reset_process : PROCESS
BEGIN
reset_in = '1';
wait for CLK_PERIOD / 2;
reset_in = '0';
wait for CLK_PERIOD * 64;
-- This means that you have 64 clock cycles to do your input/output
-- testing before the system resets itself.   Adjust to suit your needs.
END PROCESS;
-- Here you will supply the appropriate input for the two numbers to add.
-- Let each input combination sit at the appropriate place for a reasonably
-- long time.  Start at CLK_PERIOD * 4 and work your way up until the
-- outputs are stable and what you'd expect them to be.

Once you have written and simulated the testbench, answer the following questions:

-What is the signal CE used for in the core?  That is, briefly describe it's function.
-Why is the SUM output one bit larger than either the A or B inputs?

When you have completed the lab, turn in the following with your report:

-What was asked of you from the tutorial.

-A printed copy of your VHDL project, including the top-level file,
your completed VHDL testbench, and a printout of your ModelSim simulation.