Buses and
Arbiters
A bus is a communication
path way connecting two or more devices. A key characteristic of a bus
is that it is a shared transmission medium. Multiple devices connect
to the bus, and a signal transmitted by any one device is available
for reception by all other devices attached to the bus. Several considerations
on the buses design need to be done, the most important are[1]:
- Multiple-bus hierarchies
as a method to improve the performance when a great number of devices
are connected to the bus
- Method of arbitration
to determine the control over the bus, since multiple devices are
connected to it and have access to it at the same time
- Timing; which refers to
the way in which events are coordinated on the bus, either synchronous
or asynchronous
Multiple buses and arbiters
cores are available to our embedded system design:
- Processor Local Bus (PLB)
- Arbitration for up to
16 masters
- 64-bit and 32-bit masters
and slaves
- IBM PLB compliant
- On-Chip Peripheral Bus
(OPB)
- Includes arbiter with
dynamic or fixed priorities and bus parking
- Parameterized I/O for
any number of masters or slaves
- IBM OPB compliant
- Device Control Register
Bus (DCR)
- Supports one master and
multiple slaves
- Daisy chain connections
for the DCR data bus
- Required OR function of
the DCR slaves acknowledge signal
- Local Memory Bus (LMB)
- Microblaze single-master
Local Memory Bus
If communication is needed
between buses, bridges are available:
- PLB to OPB
- Decode up to 4 different
address ranges
- 32-bit or 64-bit PLB
slave, 32-bit OPB master
- Burst and non-burst
transfer, cache-line transactions
- OPB to PLB
- 64-bit PLB master,
32-bit OPB slave
- Burst and non-burst
transfer, cache-line transactions
- BESR and BEAR
- OPB (slave) to DCR (master)
- Memory mapped DCR
control
- OPB to OPB
- Allows further OPB
partitioning
[1] Computer Organization
& Architecture, Designing for performance. W. Stallings
[2] EDK workshop at UNM, John Linn, Rick Moleres
[3] On-Chip Peripheral Bus V2.0 with OPB Arbiter, Product Specification
(DS401, v2.2)
[4] Processor Local Bus, Product Specification (DS400, v1.3)
[5] Device Control Register Bus, Product Specification (DS402, v1.2)