Digilent
Spartan2E: This is fairly simple lab; it's composed by a microblaze
soft processor, memory, jtag module, general purpose inputs and outputs
and a uart that will be use to display a "Hello word" message
using hyperterminal. Its primary goal is to make us familiar with
EDK and microblaze.
AFX
V1000: This lab is built on the first one. A timer and an interrupt
controller have been added. The primary goal for this lab is to introduce
the concept of interrupts and how to work with them in the microblaze
environment.
ML1
Flash: This lab will include an external memory controller. The
goal is to store our microprocessor program in an outside-the-chip
flash memory and configure the system to program the FPGA automatically
when the power is turned on.
Lab
1 - ML300 board: This lab includes a ppc405 processor, a couple
buses, a jtag controller, an on-chip memory block, general purpose
input and outputs and a uart. It will basically show a hello-word-type
message using hyperterminal and display data using onboard leds.
Lab
2- ML300 board: This lab is built on the first one. We are adding
an interrupt controller and a timer to introduce interrupts on the
context of the PowerPC processor.
Lab
3- ML300 board: This lab includes an external memory (the program
is too big to fit in the internal Virtex2 Pro memory) and an Ethernet
core. A TCP/IP stack is used and the system is able to respond to
ICMP (ping) packets. Interrupts are used and the program is split
in several files. XilNet library is introduced and used in this lab.
(New!!) Lab 4-ML300 board: Step by step guide to build a ML300 project using EDK 7.1 and ISE 7.1 by James Lucero, senior ECE-UNM undergraduate student. The project creates a simple system and adds a PS2 core. The lab is delivered in PDF version and it is intend as an introduction to EDK 7.1 and the ML300 board.
(New!!) Lab 5 - ML300 board: Step by step guide on adding a TFC core to a PPC405 project by James Lucero, senior ECE-UNM undergraduate student.
(New!!) Lab 6 - ML300 board: Step by step guide creates a core using Sysgen and adds it to a PPC 405 using OPB and PLB interfaces. It uses Sysgen 7.1, EDK 7.1 and ISE 7.1.