This lab project builds on the previous two Microblaze labs. This is the first lab that will use EDK 3.2 SP1 but the theory upon which the previous two tutorials were written on is still the same. It is highly recommended that you walk through the Digilent and AFX1000 tutorials before you begin this tutorial. This lab will use the ML1 platform to develop a bootloader from flash memory. Here is a picture of the ML1 platform.
The overall thought will be that we will use XPS to develop our microprocessor. This microprocessor we will store into the onboard PROM so that when power is applied it will be downloaded and developed into the VirtexE FPGA. Once this is done, it will then use its' external memory controller to go flash memory to obtain its' application code. When the processor is finally complete it will flash one of the LEDs on the board and print "Go Lobos" to the screen through the UART.
What this project will do is first show you how to complete the XPS portion of the project. This part encompasses development of the entire microprocessor system. Once this is done, you will be shown how it is placed into external PROM. The application code will be paced into a flash memory location. Upon power up of the system, the required file necessary to develop the microprocessor onto the VirtexE FPGA will be downloaded from a PROM. This will cause the microprocessor to be developed. The microprocessor will then go to a flash location to access its application code. We will be using two flash banks to store the microprocessor application code. We are using two banks since each bank is 16-bits and we desire 32-bits. We will be breaking our data bits into 31-16 and 15-0 segments. We will be using a 32-bit bus interface and a memory width of 32-bits. Our memory width must be less than or equal to the OPB data bus width.
The first step will be the development of the microprocessor system. Here is a picture of how that will look.
Here are the overall steps that the project should follow as it develops.
Since the largest change from previous tutorials to this one is the addition of the external memory controller and the StrataFlash, it is a good idea to spend a few minutes discussing them. The datasheet for the EMC (external memory controller) has a lot of good information on this subject. One of the biggest things I noted that can't be forgotten is the fact that the EMC is big-endian and the StrataFlash is little-endian.
A good deal of this is explained by examining the "connection to 32-bit memory using 2 StrataFlash parts" table from the EMC manual. As you can see, DN0 (bank 0) data bus for the EMC goes from 0 to 15 where the StrataFlash data bus goes from 15 to 0. Begin the tutorial by launching EDK XPS.
I chose the following settings for my project based on the Xilinx FPGA on my board. The directory choice is optional. Once you say OK you will be asked a question about using a blank MHS file. Go ahead and choose "OK."
The next step is to add peripherals to the project. The peripherals are what will allow me to have bus controllers and other items that will be connected to buses. Shown below is the memory map for this project. It tells you how memory addresses are to be allocated.
Now it is necessary to select each instance of the devices and add them to the project.
You will note that I have changed the instance names to reflect my spreadsheet names. These names should be meaningful since they will be useful in troubleshooting efforts later. Next it is necessary to choose buses and make bus to peripheral connections.
I have chosen to add two of the "lmb_v10.a" buses (one for data and one for instructions) and one of the "opb_v20.b" buses for connecting the OPB devices to. Click on OK. Choose to regenerate the diagram based on the mhs file and you will see one of the really neat features between the 3.2 version of EDK and the previous versions.
The software now gives you a pictorial view of how your project is interconnected. By highlighting on one of the boxes (as I have done with the mblaze) you can see its connections, its version information and you even have access to the PDF document associated with it.
This lab is still under construction!.. final part is comming soon!
alnz | UNM - XUP